1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a word line driving signal control circuit, a semiconductor memory apparatus having the same, and a word line driving method.
2. Related Art
A semiconductor memory apparatus includes memory cells with high capacity, and has a memory area divided into a plurality of mats having a designated unit size for efficient control.
FIG. 1 is a diagram explaining an example of a memory area applied to a semiconductor memory apparatus.
The memory area may be divided into a plurality of mats mat 0 to mat n. For example, mats may be provided for memory cells connected between a plurality of word lines and a plurality of bit lines. The number of mats may be a refresh unit (8 k, for example 1) divided by a row size (the number of word lines) of a mat.
In the case of a memory area with a row size of 512, since 8 k/512=16, 16 mats may be provided. When a column size is 512, a unit mat size is 256 kb (=512 rows*512 columns).
With the high integration of a semiconductor memory apparatus, a unit mat size has increased. However, as the mat size increases, bit line loading may increase to a point where a normal operation may not be possible. Accordingly, there is a limitation in the selection of the mat size. Typically a mat size of 640 or 768 is employed.
FIG. 2 is a diagram explaining another example of a memory area applied to a semiconductor memory apparatus. A row size of 768 will be used in the following examples, but it should be noted that the invention need not be limited to that row size.
10 mats (mat 0 to mat m, m=9) corresponding to a refresh unit (8 k, for example) divided by a row size of 768 may be provided. In order to form a redundant mat of memory cells, which are coupled to 512 word lines in one mat, it is necessary to add 256 word lines and memory cells corresponding to the 256 word lines. For the redundant mat formed in this way, only the 512 word lines are actually used for an operation, and the additionally formed 256 word lines are not actually used.
Since a semiconductor memory apparatus includes a plurality of memory cells, if a defect occurs in one of the plurality of memory cells, the semiconductor memory apparatus has no value as a product. Thus, when a redundancy memory cell is additionally provided and a defect occurs, a failed cell is replaced with a redundancy memory cell.
To this end, a failed cell is found through a test process. Then, an address signal corresponding to the failed cell is replaced with an address signal of a redundancy cell.
FIG. 3 is a configuration diagram of a general word line driving signal control circuit.
A word line driving signal control circuit 10 includes a fuse unit 12 and a repair determination unit 14.
The fuse unit 12 includes a plurality of fuses. The fuse unit 12 outputs a redundancy enable signal XHITB according to the state of a fuse corresponding to an address signal BXAR in response to the address signal BXAR, a fuse enable signal FEN, and a bank active signal BACT.
The repair determination unit 14 outputs a normal word line driving signal WLEN or a redundancy word line driving signal RWLEN in response to the redundancy enable signal XHITB, the bank active signal BACT, and a word line off signal WLOFF. The word line off signal WLOFF is a word line control signal, and provides a normal word line driver or a redundancy word line driver with the normal word line driving signal WLEN or the redundancy word line driving signal RWLEN.
However, since a redundancy cell is fabricated in the same manner as a normal cell, a defect may also occur in the redundancy cell. If a defect occurs in the redundancy cell, it is not possible to repair a corresponding memory apparatus.
As described above, after some failed cells of a plurality of memory cells are replaced with redundancy cells, if a defect occurs in the redundancy cells, a memory apparatus may be discarded, resulting in the reduction of a product yield and the waste of a resource.